Write management on flash memory

ABSTRACT

A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser.No. 16/735,709, filed on 2020 Jan. 7, the contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a flash memory, and more particularly,to a method for managing blocks in a flash memory that are going to bewritten, and an associated controller and storage device.

2. Description of the Prior Art

In general, the flash memory controller searches for an available erasedblock in the flash memory according to the writing command delivered bythe host, in order to perform data writing. However, if being under theerase state for too long, the flash memory unit may suffer from someunrecoverable physical damages. Therefore, there is a need for a novelwriting management scheme to prevent the above problem.

SUMMARY OF THE INVENTION

In view of the above, an objective of the present invention is toprovide a writing management scheme of a flash memory. The presentinvention uses a portion of blocks divided from a flash memory as aspare pool. The controller selects blocks from the spare pool for datawriting in order to complete the writing command delivered by the host.Note that the aforementioned spare pool only preserves very a limitedamount of erased blocks, and the rest of space are used to preservewritten blocks (e.g. programmed blocks). When the controller receiveswriting commands from the host, the controller will search for erasedblocks preserved in the spare pool in order to write data into them.After the writing is finished, the controller will perform erasingoperations on one or more written blocks in the spare pool, and takethem as new preserved blocks. In this way, the amount of erased blockswithin the blocks of the flash memory can be decreased.

In another aspect, the controller creates the time file (e.g. thetimestamp) thereof for each erased block preserved in the spare pool, inorder to for monitor the duration the block remains in the erase state.Once the duration of said erased block exceeds a specific threshold, thecontroller will perform writing on this erased block, and choose one ormore blocks among the written blocks in the spare pool, in order toreduce the extent of physical damages.

An embodiment of the present invention proposes a method for managing aflash memory module. The flash memory module comprises a plurality ofblocks, wherein a portion of the plurality of blocks belongs to a sparepool. The method comprises: preserving at least one erased block in thespare pool to facilitate a writing operation, wherein the spare poolcomprises at least one erased block and a plurality of written blockswith invalid data, and a number of the written blocks is greater than anumber of the at least one erased block; monitoring an erasing period ofthe at least one erased block; and when the erasing period exceeds athreshold, moving valid data stored in a certain block that does notbelong to the spare pool to the at least one erased block and removingthe at least one erased block from the spare pool.

An embodiment of the present invention proposes a controller formanaging a flash memory module, wherein the flash memory modulecomprises a plurality of blocks, a portion of the plurality of blocksbelongs to a spare pool. The controller comprises a storage unit and aprocessing unit. The storage unit is arranged to store a program code.The processing unit is coupled to the storage unit, and is arranged toread the program code from the storage unit in order to execute theprogram code to perform following operations: preserving at least oneerased block in the spare pool to facilitate a writing operation,wherein the spare pool comprises at least one erased block and aplurality of written blocks with invalid data, and a number of thewritten blocks is greater than a number of the at least one erasedblock; monitoring an erasing period of the at least one erased block;and when the erasing period exceeds a threshold, moving valid datastored in a certain block that does not belong to the spare pool to theat least one erased block and removing the at least one erased blockfrom the spare pool.

An embodiment of the present invention proposes a storage device whichcomprises a flash memory module and a controller. The flash memorymodule comprises a plurality of blocks, wherein a portion of theplurality of blocks belongs to a spare pool. The controller is arrangedto access the flash memory module, and comprises a storage unit and aprocessing unit. The storage unit is arranged to store a program code.The processing unit is coupled to the storage unit, wherein theprocessing unit is arranged to read the program code from the storageunit in order to execute the program code, and thereby performsfollowing operations: preserving at least one erased block in the sparepool to facilitate a writing operation, wherein the spare pool comprisesat least one erased block and a plurality of written blocks with invaliddata, and a number of the written blocks is greater than a number of theat least one erased block; monitoring an erasing period of the at leastone erased block; and when the erasing period exceeds a threshold,moving valid data stored in a certain block that does not belong to thespare pool to the at least one erased block and removing the at leastone erased block from the spare pool.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating the architecture of a storage device,an associated controller and a flash memory module according to anembodiment of the present invention.

FIG. 2 is a diagram illustrating the interactions between a flash memorymodule and a spare pool according to an embodiment of the presentinvention.

FIG. 3 is a flowchart illustrating a method for managing the writing ofblocks of a flash memory according to an embodiment of the presentinvention.

FIG. 4 is a diagram illustrating the interactions between a main controlcommand and a memory-operating command according to an embodiment of thepresent invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present embodiments. Itwill be apparent, however, to one having ordinary skill in the art thatthe specific detail need not be employed to practice the presentembodiments. In other instances, well known materials or methods havenot been described in detail in order to avoid obscuring the presentembodiments.

Additionally, any examples or illustrations given herein are not to beregarded in anyway as restrictions on, limits to, or express definitionsof any term or terms with which they are utilized. Instead, theseexamples or illustrations are to be regarded as being described withrespect to one particular embodiment and as being illustrative only.Those of ordinary skill in the art will appreciate that any term orterms with which these examples or illustrations are utilized willencompass other embodiments which may or may not be given therewith orelsewhere in the specification and all such embodiments are intended tobe included within the scope of that term or terms. Language designatingsuch non-limiting examples and illustrations includes, but is notlimited to: “for example,” “for instance,” “e.g.,” and “in oneembodiment.”

The flowchart and block diagrams in the flow diagrams illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present embodiments. In this regard, each block inthe flowchart or block diagrams may represent a module, segment, orportion of code, which comprises one or more executable instructions forimplementing the specified logical function(s). It will also be notedthat each block of the block diagrams and/or flowchart illustrations,and combinations of blocks in the block diagrams and/or flowchartillustrations, may be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions. These computerprogram instructions may also be stored in a computer-readable mediumthat can direct a computer or other programmable data processingapparatus to function in a particular manner, such that the instructionsstored in the computer-readable medium produce an article of manufactureincluding instruction means which implement the function/act specifiedin the flowchart and/or block diagram block or blocks.

FIG. 1 illustrates the architecture of a storage device 100, anassociated controller 120 and a flash memory module 130 according to anembodiment of the present invention. As shown in FIG. 1, the storagedevice 100 comprises a controller 120 and a flash memory module 130, andis controlled by a host device 200, wherein the storage device 100 maybe part of the host device 200. The host device 200 may comprise atleast one central processing unit (CPU) (not shown) to controloperations of the host device 200 via operating an operating system (OS)and an application, in order to interact with peripheral devices. Thestorage device 100 may provide storage space for the host device 200 aswell as program codes and the data necessary for the storing operationsof the OS and various applications. Examples of the host device 50 maycomprise (but are not limited to): a multifunctional mobile phone,tablet, wearable device and personal computer (such as a desktop orlaptop computer). Examples of the storage device 100 may comprise (butare not limited to): solid state drives (SSD) and various types ofembedded storage devices (e.g. the storage devices that conform to theUFS or EMMC specifications).

The controller 120 may access the flash memory module 130. In oneembodiment, the flash memory module 130 may be a stereo (also dubbed as3D) NAND flash, and may comprise at least one flash memory chip, butthis is not meant to be a limitation of the present invention. Eachflash memory chip may comprises a plurality of blocks, and thecontroller 120 may use “block” as the unit of performs data erasing onthe flash memory module 130. Further, a block may record a specificnumber of pages, and the controller 120 may use “page” as the unit towrite data into the flash memory module 130.

The controller 120 may comprise a processing circuit (e.g. themicroprocessor 122 and the storage unit 124), such as a read only memory(ROM). The ROM 124 is mainly used for storing program codes and specificdata, and the microprocessor 122 is used for executing program codes tocontrol the access of the flash memory module 130. Further, thecontroller 120 may comprise one or more interface logics for assistingthe operations described later, such as control logics, buffers, etc.,but those elements are omitted here for brevity. After reading thefollowing contents, one skilled in the art should be readily to know howto properly combine well known circuits with the circuit elements andarchitectures disclosed in the present invention, and can therebyimplement various operations and associated applications mentioned inthe embodiments of the present invention.

In this embodiment, the host device 200 may indirectly access thestorage device 100 by transmitting a host command and the correspondinglogic address to the controller 120. The controller 120 receives thehost command (e.g. a reading command or a writing command) as well asthe logic address, and translates the host command into amemory-operating command and then uses the operating command to controlthe flash memory module 130 to perform reading, writing, programing orerasing on memory units, pages or blocks of a specific physical addressin the flash memory module 130. Moreover, the controller 120 may alsoexecute the program code, and/or execute a series of operationsaccording to data in the storage unit 124 in order to perform a seriesof operations to implement the specific operation mentioned in thefollows.

FIG. 2 is a diagram illustrating the interactions between a flash memorymodule and a spare pool according to an embodiment of the presentinvention. As shown in FIG. 2, the flash memory module 130 comprisesmultiple blocks, and these blocks may be distributed in the flash memorychips 130_1-130_N. In addition, some blocks in the flash memory module130 may be categorized as a spare pool 138. The spare pool 138 maycomprise the blocks SB0-SBQ, and theses blocks may either store no dataor may store invalid data (e.g. which is also stored in other blocks anddoes not need to be further updated). In the present invention, all thewriting commands issued from the host device 200 will trigger thecontroller 120 to select one or more blocks from the spare pool 138 andperform writing (e.g. writing data into one or more pages of a block)according to the data comprised in the writing commands that are issuedfrom the host device 200. When one or more blocks are written due to thewriting commands issued from the host device 200, those blocks will beremoved from the spare pool 138, and then the controller 120 will selectone or more blocks storing invalid data among the blocks DB0-DBK whichare not currently included in the spare pool 138, in order to compensatethe spare pool 138.

In the present invention, the controller 120 will preserve at least oneerased block (e.g. block SB_0) which is in the erase state in the sparepool 138, and this is because erasing a block may consume a considerableamount of time. However, the lagging resulted from the writing operationmay be mitigated by performing erasing operations. When the host device200 issues writing commands to the controller 120, the controller 120will write the data issued from the host into the erased block SB_0which is preserved in the spare poop 138. Further, before the hostdevice 200 issues the next writing command to the controller 120, thecontroller 120 will seek for at least one block (e.g. the block SB_3)from the written/programmed blocks SB_1-SB_Q in the spare poop 138, andthen erase the at least one block for follow-up writing operations.

As mentioned above, however, if a block stays in the erase state toolong, units thereof might suffer from irreversible physical damages.Hence, the method of the present invention may manage the erased blocksin the spare pool, and after a certain amount of time, those erasedblocks will be written with data so as to prevent potential damages.Please refer to the FIG. 3, which is a flowchart illustrating a methodfor managing writing of blocks of a flash memory according to anembodiment of the present invention, and can be summarized as follows:

Step 210: Preserve at least one erased block.

Step 220: Create a timestamp of the at least one erased block.

Step 230: Determine whether the erasing period of the at least oneerased block exceeds a threshold.

Step 240: Write the at least one erased block.

Step 250: Select at least one written block for replacing the erasedblock.

In Step 210, the controller 120 performs erasing an operation on atleast one written block in the spare poop 138, to make the at least onewritten block (e.g. SB_7) be converted into an erase state from awritten dfcstate (e.g. a programmed state), as a preparation for futurewriting operations. Step 210 may take place before the host device 200issues a writing command, or after the controller 120 performs writingon another erased block. In Step 220, the controller 120 creates atimestamp of the at least one erased block. In Step 230, the controller120 refers to the time information and system time in the timestamp todetermine whether the time the at least one erased block is in the erasestate exceeds a threshold. This step is meant to protect erased blocksfrom suffering, to prevent it from suffering unrecoverable physicaldamage. If the determination result in Step 230 is “Yes”, the flow goesto Step 230; if not, the flow stays in the current step. In Step 240,since the controller 120 already finds that the erasing period of the atleast one erased block has exceeded the threshold, which suggests thatthe erased block is in danger of being damaged, the controller 120 willperform writing on the at least one erased block to convert the blockfrom the erase state to the written state, in order to prevent somepotential damages.

Further, according to an embodiment, the controller 120 may utilize theopportunity of writing to erased blocks, and perform a garbagecollection operation in the meantime. The controller 120 writes to theat least one erased block according to the data collected from the validpages of the blocks DB0-DBK, in order to convert the at least one erasedblock into a written block. After that, the flow goes to Step 250, thecontroller 120 will search for at least one written block (e.g. SB_4) inthe spare poop 138 to replace the aforementioned at least one erasedblock, and then the flow goes back to Step 210 to perform erasingoperation on the block, as preparations for the follow-up writingcommand.

As can be seen from the above, the present invention may effectivelyprotect the memory unit in the flash memory module 130, in order toprevent it from being damaged due to staying in the erase state for toolong. In another aspect, since the present invention has preserved theerased block in the spare pool, the latency of writing data can bereduced, that is, there is no need for further waiting for the time oferasing the written block.

Moreover, a feature of the present invention is about how the controller120 controls the flash memory module 130, which can be referred to FIG.4. FIG. 4 is a diagram illustrating the interactions between a maincontrol commands and a memory-operating command according to anembodiment of the present invention. When the host device 200 issues amain control command (e.g. a read command or a write command) to thecontroller 120, the controller 120 may access the flash memory chips130_1-130_N in the flash memory module 130 according to the accesstypes, addresses and related data comprised in the main control commandand converting the above information into a correspondingmemory-operating command.

In the present invention, the management on the erased block isindependent from the main control command of the host device 200, and isperformed according to the timestamp of erased blocks. Hence, even ifthe host device 200 does not issue the main control command to thecontroller 120, events (such as an alternative operation of the erasedblocks as well as the garbage collection operation) may still betriggered due to the timestamp of the erased blocks in the spare pool138 exceeding the threshold. Hence, in an embodiment, the controller 120may issue the following consecutive command sequences to the flashmemory chip 130_1-130_N without receiving any access command from thehost device 200:

Read: 00h ALE 30h

Write: 80h ALE 10h

Erase: 60h ALE D0h

Initially, if the timestamp of an erased block exceeds a duration limit,Step 240 in the aforementioned process will be triggered to write toerased blocks. As mentioned above, writing to erased blocks may alsotrigger the garbage collection operation in the meantime. Hence, thefirst reading command in the aforementioned command sequence is toperform the garbage collection operation, in order to read data from thevalid pages in the blocks DB0-DBK that located outside the spare pool138. The readout data will later be transmitted to the controller 120 tobe processed with error correction. Next, the processed data (i.e. thesecond written command in the aforementioned command sequence) will bewritten to erased blocks. Lastly, the flow goes to Step 250 to selectanother block from the spare pool to erase, as an alternative of theerased blocks, i.e. the third erase command in the aforementionedcommand sequence. As can be further seen from the timing diagram inbottom of FIG. 4, the main control command may trigger the controller120 to generate associated the memory-operating command, but thecontroller 120 will remain periodically generating spontaneousmemory-operating commands. Therefore, a feature of the present inventionlies in that even if the host device 200 has not yet to issue an accesscommand to the controller 120, the controller 120 can nonethelessspontaneously issue successive command sequences (such as those forreading, writing and erasing) to the flash memory module 130.

As mentioned above, via proper management for the spare pool, thepresent invention may effectively reduce the latency of writing data (bypreserving at least one erased block in the spare pool), and may alsoprevent potential physical damages (by limiting the time the blocks stayin the erase state). Meanwhile, the management mechanism may furthercombine with the garbage collection operation to perform more suitablewriting on the erased blocks or to displace them.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A method for managing a flash memory module, theflash memory module comprises a plurality of blocks, wherein a portionof the plurality of blocks belongs to a spare pool, and the methodcomprises: preserving at least one erased block in the spare pool tofacilitate a writing operation, wherein the spare pool comprises atleast one erased block and a plurality of written blocks with invaliddata, and a number of the written blocks is greater than a number of theat least one erased block; monitoring an erasing period of the at leastone erased block; and when the erasing period exceeds a threshold,moving valid data stored in a certain block that does not belong to thespare pool to the at least one erased block and removing the at leastone erased block from the spare pool.
 2. The method of claim 1, whereinthe step of monitoring the erasing period of the at least one erasedblock comprises: creating a timestamp associated with the at least oneerased block; and periodically performing comparison on the thresholdaccording to time information in the timestamp.
 3. The method of claim1, wherein when the erasing period exceeds the threshold, the methodfurther comprises: choosing a first block from the plurality of writtenblocks in the spare pool, and performing an erasing operation on thefirst block; and adding a second block storing invalid data to the sparepool after the at least one erased block is removed.
 4. The method ofclaim 1, further comprising: performing a garbage collection operationon a plurality of blocks in the flash memory module; and when theerasing period exceeds the threshold, utilizing recycled data outputtedby the garbage collection operation to perform writing on the at leastone erased block.
 5. The method of claim 1, further comprising: if anaccess command delivered by a host is not received, automaticallyreading specific data from the flash memory module, and writing thespecific data back to the flash memory module.
 6. A controller formanaging a flash memory module, wherein the flash memory modulecomprises a plurality of blocks, a portion of the plurality of blocksbelongs to a spare pool, and the controller comprises: a storage unit,arranged to store a program code; and a processing unit, coupled to thestorage unit, the processing unit arranged to read the program code fromthe storage unit in order to execute the program code to performfollowing operations: preserving at least one erased block in the sparepool to facilitate a writing operation, wherein the spare pool comprisesat least one erased block and a plurality of written blocks with invaliddata, and a number of the written blocks is greater than a number of theat least one erased block; monitoring an erasing period of the at leastone erased block; and when the erasing period exceeds a threshold,moving valid data stored in a certain block that does not belong to thespare pool to the at least one erased block and removing the at leastone erased block from the spare pool.
 7. The controller of claim 6,wherein the processing unit executes the program code to create atimestamp associated with the at least one erased block and periodicallyperform comparison on the threshold according to time information in thetimestamp.
 8. The controller of claim 6, wherein when the erasing periodexceeds the threshold, the processing unit executes the program code tochoose a first block from the plurality of written blocks in the sparepool in order to perform an erasing operation on the first block; andwhen the erasing period exceeds the threshold, the processing unitexecutes the program code to add a second block storing invalid data tothe spare pool after the at least one erased block is removed.
 9. Thecontroller of claim 6, wherein the processing unit executes the programcode to perform a garbage collection operation on a plurality of blocksin the flash memory module; and when the erasing period exceeds thethreshold, the processing unit utilizes recycled data outputted by thegarbage collection operation to perform writing on the at least oneerased block to execute the alternative operation.
 10. The controller ofclaim 6, wherein the controller is controlled by a host, and theprocessing unit executes the program code to automatically read specificdata from the flash memory module when an access command delivered bythe host is not received, and write the specific data back to the flashmemory module.
 11. A storage device, comprising: a flash memory module,comprising a plurality of blocks, wherein a portion of the plurality ofblocks belongs to a spare pool; and a controller, arranged to access theflash memory module, and comprising: a storage unit, arranged to store aprogram code; and a processing unit, coupled to the storage unit,wherein the processing unit is arranged to read the program code fromthe storage unit in order to execute the program code, and therebyperform following operations: preserving at least one erased block inthe spare pool to facilitate a writing operation, wherein the spare poolcomprises at least one erased block and a plurality of written blockswith invalid data, and a number of the written blocks is greater than anumber of the at least one erased block; monitoring an erasing period ofthe at least one erased block; and when the erasing period exceeds athreshold, moving valid data stored in a certain block that does notbelong to the spare pool to the at least one erased block and removingthe at least one erased block from the spare pool.
 12. The storagedevice of claim 11, wherein the controller is arranged to create atimestamp associated with the at least one erased block; and thecontroller periodically performs comparison on the threshold accordingto time information in the timestamp.
 13. The storage device of claim11, wherein when the erasing period exceeds the threshold, thecontroller is arranged to choose a first block from the plurality ofwritten blocks in the spare pool in order to perform an erasingoperation on the first block; and when the erasing period exceeds thethreshold, the controller is arranged to add a second block storinginvalid data to the spare pool after the at least one erased block isremoved.
 14. The storage device of claim 13, wherein when the erasingperiod exceeds the threshold, the controller performs a garbagecollection operation on a plurality of blocks in the flash memorymodule; and the controller utilizes recycled data outputted by thegarbage collection operation to perform writing on the at least oneerased block.
 15. The storage device of claim 14, wherein the controlleris controlled by a host, and when an access command delivered by thehost is not received, the controller automatically reads specific datafrom the flash memory module, and writes the specific data back to theflash memory module.